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| HY57V641620HG 4 Banks x 1M x 16Bit Synchronous DRAM D E S C R IP T IO N The Hynix HY57V641620HG is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V641620HG is organized as 4banks of 1,048,576x16. HY57V641620HG is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a 2N rule.) FEATURES * * * Single 3.30 . 3 V power supply Note) * * * Auto refresh and self refresh 4096 refresh cycles / 64ms Programmable Burst Length and Burst Type - 1, 2, 4, 8 or Full page for Sequential Burst All device pins are compatible with LVTTL interface JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin pitch * All inputs and outputs referenced to positive edge of system clock - 1, 2, 4 or 8 for Interleave Burst * Programmable CAS Latency ; 2, 3 Clocks * * Data mask function by UDQM or LDQM Internal four banks operation O R D E R IN G IN F O R M A T IO N Part No. HY57V641620HGT-5/55/6/7 HY57V641620HGT-K HY57V641620HGT-H HY57V641620HGT-8 HY57V641620HGT-P HY57V641620HGT-S HY57V641620HGLT-5/55/6/7 HY57V641620HGLT-K HY57V641620HGLT-H HY57V641620HGLT-8 HY57V641620HGLT-P HY57V641620HGLT-S C lock Frequency 200/183/166/143MHz 133MHz 133MHz Power Organization Interface Package Normal 125MHz 100MHz 100MHz 200/183/166/143MHz 133MHz 133MHz Low power 125MHz 100MHz 100MHz 4Banks x 1Mbits x16 LVTTL 400mil 54pin TSOP II N o t e : V D D ( M in ) o f H Y 5 7 V 6 4 1 6 2 0 H G ( L ) T - 5 /5 5 / 6 i s 3 . 1 3 5 V This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.5/Jun.01 HY57V641620HG P IN C O N F IG U R A T IO N VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 VDD LDQM /WE /CAS /RAS /CS BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54pin TSOP II 400mil x 875mil 0.8mm pin pitch 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 V SS DQ15 V SSQ DQ14 DQ13 V DDQ DQ12 DQ11 V SSQ DQ10 DQ9 V DDQ DQ8 V SS NC UDQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 V SS P IN D E S C R IP T IO N PIN PIN NAME D E S C R IPTION The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh Enables or disables all inputs except CLK, CKE and DQM S e l e c t s b a n k t o b e a c t i v a t e d d u r i n g R A S activity S e l e c t s b a n k t o b e r e a d / w r i t t e n d u r i n g C A S activity Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA7 Auto-precharge flag : A10 CLK Clock CKE Clock Enable CS Chip Select BA0,BA1 Bank Address A0 ~ A11 Address Row Address Strobe, R A S , C A S, W E Column Address Strobe, Write Enable LDQM, UDQM DQ0 ~ DQ15 V D D /V S S V D D Q /V S S Q NC Data Input/Output Mask Data Input/Output Power Supply/Ground Data Output Power/Ground No Connection R A S , C A S and W E define the operation Refer function truth table for details Controls output buffers in read mode and masks input data in write mode Multiplexed data input / output pin Power supply for internal circuits and input buffers Power supply for output buffers No connection Rev. 0.5/Jun.01 2 HY57V641620HG F U N C T IO N A L B L O C K D IA G R A M 1Mbit x 4banks x 16 I/O Synchronous DRAM Self refresh logic & timer Internal Row counter CLK Row active 1Mx16 Bank 3 Row Pre Decoders 1Mx16 Bank 2 X decoders CKE CS 1Mx16 Bank 1 X decoders 1Mx16 Bank 0 State Machine X decoders RAS DQ0 DQ1 Sense AMP & I/O Gate X decoders I/O Buffer & Logic Memory Cell Array CAS WE UDQM refresh Column Active Column Pre Decoders DQ14 DQ15 LDQM Y decoders Column Add Bank Select Counter A0 A1 Address Registers Address buffers Burst Counter A11 BA0 BA1 CAS Latency Mode Registers Data Out Control Pipe Line Control Rev. 0.5/Jun.01 3 HY57V641620HG A B S O L U T E M A X IM U M R A T IN G S P a r a m e ter Ambient Temperature Storage Temperature Voltage on Any Pin relative to V S S Voltage on V D D relative to V S S Short Circuit Output Current Power Dissipation Soldering Temperature T i m e TA TS T G V IN, V O U T VDD, VD D Q IO S PD TSOLDER Symbol 0 ~ 70 -55 ~ 125 -1.0 ~ 4.6 -1.0 ~ 4.6 50 1 260 10 Rating C C V V mA W C S e c Unit N o te : O p e r a t i o n a t a b o v e a b s o l u t e m a x i m u m r a t i n g c a n a d v e r s e l y a f f e c t d e v i c e r e l i a b i l i t y D C O P E R A T IN G C O N D IT IO N P a r a m e ter Power Supply Voltage Input High Voltage Input Low Voltage Symbol VD D , VDDQ V IH V IL ( T A = 0 t o 7 0 C ) M in 3.0 2.0 V S S Q - 2.0 Typ. 3.3 3.0 0 Max 3.6 V DDQ + 2.0 0.8 Uni t V V V N o te 1,2 1,3 1,4 N o te : 1.All voltages are referenced to VSS = 0 V 2.VDD(min) of HY57V641620HG(L)T-5/55/6 is 3.135V 3.V IH (max) is acceptable 5.6V AC pulse width with 3ns of duration 4.V IL (min) is acceptable -2.0V AC pulse width with 3ns of duration A C O P E R A T IN G C O N D IT IO N P a r a m e ter AC Input High / Low Level Voltage ( T A = 0 t o 7 0 C , V D D = 3 . 3 0 . 3 V N o t e 2 , V S S = 0 V ) Symbol V I H / V IL Vtrip tR / tF Voutref CL Value 2.4/0.4 1.4 1 1.4 50 Uni t V V ns V pF Note Input Timing Measurement Reference Level Voltage Input Rise / Fall Time Output Timing Measurement Reference Level Output Load Capacitance for Access Time Measurement 1 N o te : 1. Output load to measure access time is equivalent to two TTL gates and one capacitor (50pF) For details, refer to AC/DC output circuit 2.VDD(min) of HY57V641620HG(L)T-5/55/6 is 3.135V Rev. 0.5/Jun.01 4 HY57V641620HG C A P A C IT A N C E Parameter Input capacitance CLK A0 ~ A11, BA0, BA1, CKE, C S, RAS, CAS, W E, UDQM, LDQM Data input / output capacitance DQ0 ~ DQ15 C I/O 2 6.5 pF ( T A = 2 5C , f = 1 M H z ) P in Symbol C I1 CI 2 M in 2 2.5 Max 4 5 Unit pF pF O U T P U T L O A D C IR C U IT Vtt=1.4V RT=250 Output Output 50pF 50 pF DC Output Load Circuit AC Output Load Circuit D C C H A R A C T E R IS T IC S I ( T A = 0 P a r a m e ter Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage IL I IL O VOH VOL Symbol t o 7 0 C , V DD =3.3 0 . 3 V Note3) M in. -1 -1 2.4 - Max 1 1 0.4 Unit uA uA V V Note 1 2 IO H = - 4 m A IO L = + 4 m A N o te : 1 . V I N = 0 t o 3 . 6 V , A l l o t h e r p i n s a r e n o t t e s t e d u n d e r V IN = 0 V 2.DO U T is disabled, V O U T =0 to 3.6 Rev. 0.5/Jun.01 5 HY57V641620HG D C C H A R A C T E R IS T IC S II ( T A = 0 t o 7 0 C , V D D = 3 . 3 0 . 3 V Note5 , VSS =0V) Speed Parameter Symbol Test Condition -5 Burst length=1, One bank active tR C tR C ( m i n ) , I O L = 0 m A C K E V IL(max), tC K = min C K E V IL(max), tC K = -55 -6 -7 -K -H -8 -P -S Unit N o te Operating Current ID D 1 100 95 90 85 85 85 80 80 80 mA 1 Precharge Standby Current in Power Down Mode ID D 2 P ID D 2 P S 2 2 mA mA C K E V IH ( m i n ) , C S V I H ( m i n ) , t C K = min Precharge Standby Current in Non Power Down Mode ID D 2 N S ID D 2 N Input signals are changed one time during 2clks. All other pins V DD 0.2V or 0.2V C K E V IH ( m i n ) , t C K = 15 mA 12 mA Input signals are stable. ID D 3 P ID D 3 P S C K E V IL(max), tC K = min C K E V IL(max), tC K = 6 5 mA mA Active Standby Current in Power Down Mode C K E V IH ( m i n ) , C S V I H ( m i n ) , t C K = min ID D 3 N Active Standby Current in Non Power Down Mode Input signals are changed one time during 2clks. All other pins V DD 0.2V or 0.2V C K E V IH ( m i n ) , t C K = 30 mA ID D 3 N S Input signals are stable. tC K tC K ( m i n ) , I O L = 0 m A All banks active CL=3 CL=2 170 NA 160 NA 150 NA 150 NA 20 mA Burst Mode Operating Current 150 150 120 120 120 120 mA mA mA mA uA 1 ID D 4 Auto Refresh Current ID D 5 tR R C tR R C ( m i n ) , A l l b a n k s a c t i v e 160 1 2 3 4 Self Refresh Current ID D 6 C K E 0.2V 400 N o te : 1.ID D 1 a n d I D D 4 depend on output loading and cycle rates. Specified values are measured with the output open 2.Min. of tRRC (Refresh R A S cycle time) is shown at AC CHARACTERISTICS II 3.HY57V641620HGT-6/7/K/H/P/S 4.HY57V641620HGLT-6/7/K/H/P/S Rev. 0.5/Jun.01 6 HY57V641620HG A C C H A R A C T E R IS T IC S I ( A C -5 Parameter Symbol M in C A S Latency = System clock cycle time 3 C A S Latency = 2 Max Min Max Mi n Max Min Max M in Max Mi n Max M in Max Mi n Max Min Max operating conditions unless otherwise noted) -55 -6 -7 -K -H -8 -P -S Unit Note tCK3 55 1000 55 1000 10 6 100 0 10 7 1000 10 7.5 1000 7.5 7.5 1000 10 8 1000 10 10 1000 10 10 1000 12 ns tCK2 10 ns Clock high pulse width Clock low pulse width C A S Latency = Access time from clock 3 C A S Latency = 2 tCHW tCLW 2.5 2.5 - 2.75 2.75 - 2.5 2.5 - 2.5 2.5 - 2.5 2.5 - 2.5 2.5 - 3 3 - 3 3 - 3 3 - ns ns 1 1 tAC3 - 5.4 - 5.4 - 5.4 - 5.4 - 5.4 5.4 - 6 6 - 6 ns 2 tAC2 - 6 - 6 - 6 - 6 - 5.4 6 - 6 - 6 - 8 ns Data-out hold time Data-Input setup time Data-Input hold time Address setup time Address hold time CKE setup time CKE hold time Command setup time Command hold time CLK to data output in low Z-time C A S Latency = 3 C A S Latency = 2 tOH tDS tDH tAS tAH tCKS tCKH tCS tCH tOLZ 2.5 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 1 - 2.5 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 1 - 2.7 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 1 - 2.7 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 1.5 - 2.7 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 1.5 - 2.7 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 1.5 - 3 2 1 2 1 2 1 2 1 1 - 3 2 1 2 1 2 1 2 1 1 - 3 2 1 2 1 2 1 2 1 2 - ns ns ns ns ns ns ns ns ns ns 1 1 1 1 1 1 1 1 CLK to data output in high Z-time tOHZ3 5.4 tOHZ2 5.4 5.4 5.4 5.4 5.4 3 6 6 6 ns 3 6 ns Note : 1.Assume tR / tF (input rise and fall time ) is 1ns 2.Access times to be measured with input signals of 1v/ns edge rate Rev. 0.5/Jun.01 7 HY57V641620HG A C C H A R A C T E R IS T IC S I Symbo l M in 55 -5 Max M in 55 -55 Max Mi n 60 -6 Max Mi n 62 -7 Max M in 65 -K Max Mi n 65 -H Max Mi n 68 -8 Max Min 70 -P Max Mi n 70 -S Unit Max ns Note Parameter Operation R A S Cycle Time Auto Refresh tR C tR R C tR C D 60 - 60 - 60 - 62 - 65 - 65 - 68 - 70 - 70 - ns R A S to C A S Delay 15 - 16.5 - 18 - 20 - 15 - 20 - 20 - 20 - 20 - ns R A S Active Time tR A S 38.5 100K 38.5 100K 42 100 K 42 120K 45 120K 45 120K 48 100 K 50 120K 50 120K ns RAS Precharge Time R A S to R A S Bank Active Delay C A S to C A S Delay Write Command to Data-In Delay Data-In to Precharge Command tR P 15 - 16.5 - 18 - 20 - 15 - 20 - 20 - 20 - 20 - ns tR R D 10 - 11 - 12 - 14 - 15 - 15 - 16 - 20 - 20 - ns tC C D 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - CLK tW T L 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - CLK tD P L 2 - 2 - 2 - 1 - 1 - 1 - 2 - 1 - 1 - CLK Data-In to Active Command tD A L tD Q Z tD Q M tM R D tP R O Z 3 5 - 5 - 5 - 4 - 4 - 4 - 5 - 3 - 3 - CLK DQM to Data-Out Hi-Z 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - CLK DQM to Data-In Mask 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - CLK MRS to New Command 2 - 2 - 2 - 1 - 1 - 1 - 2 - 1 - 1 - CLK Precharge to Data Output Hi-Z CAS Latency =3 3 - 3 - 3 - 3 - 3 - 3 - 3 - 3 - 3 - CLK CAS Latency =2 tP R O Z 2 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - CLK Power Down Exit Time tP D E tS R E tR E F 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - CLK Self Refresh Exit Time 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - CLK 1 Refresh Time - 64 - 64 - 64 - 64 - 64 - 64 - 64 - 64 - 64 ms N o te : 1. A new command can be given tRRC after self refresh exit Rev. 0.5/Jun.01 8 HY57V641620HG D E V IC E O P E R A T IN G O P T IO N T A B L E H Y 5 7 V 6 4 1 6 2 0 H G (L)T-5 C A S Latency 200MHz(5ns) 183MHz(5.5ns) 166MHz(6ns) 3CLKs 3CLKs 3CLKs tRCD 3CLKs 3CLKs 3CLKs tRAS 7CLKs 7CLKs 7CLKs tRC 10CLKs 10CLKs 10CLKs tRP 3CLKs 3CLKs 3CLKs tAC 5.4ns 5.4ns 5.4ns tO H 2.5ns 2.5ns 2.7ns H Y 5 7 V 6 4 1 6 2 0 H G (L)T-55 C A S Latency 183MHz(5.5ns) 166MHz(6ns) 143MHz(7ns) 3CLKs 3CLKs 3CLKs tRCD 3CLKs 3CLKs 3CLKs tRAS 7CLKs 7CLKs 7CLKs tRC 10CLKs 10CLKs 10CLKs tRP 3CLKs 3CLKs 3CLKs tAC 5.4ns 5.4ns 5.4ns tO H 2.5ns 2.7ns 2.7ns H Y 5 7 V 6 4 1 6 2 0 H G (L)T-6 C A S Latency 166MHz(6ns) 143MHz(7ns) 133MHz(7.5ns) 3CLKs 3CLKs 2CLKs tRCD 3CLKs 3CLKs 3CLKs tRAS 7CLKs 6CLKs 6CLKs tRC 10CLKs 9CLKs 9CLKs tRP 3CLKs 3CLKs 3CLKs tAC 5.4ns 5.4ns 5.4ns tO H 2.7ns 2.7ns 2.7ns H Y 5 7 V 6 4 1 6 2 0 H G (L)T-7 C A S Latency 143MHz(7ns) 133MHz(7.5ns) 100MHz(10ns) 3CLKs 3CLKs 2CLKs tRCD 3CLKs 3CLKs 2CLKs tRAS 6CLKs 6CLKs 5CLKs tRC 9CLKs 9CLKs 7CLKs tRP 3CLKs 3CLKs 2CLKs tAC 5.4ns 5.4ns 6ns tO H 2.7ns 2.7ns 3ns H Y 5 7 V 6 4 1 6 2 0 H G (L)T-K C A S Latency 133MHz(7.5ns) 125MHz(8ns) 100MHz(10ns) 2CLKs 3CLKs 2CLKs tRCD 2CLKs 3CLKs 2CLKs tRAS 6CLKs 6CLKs 5CLKs tRC 8CLKs 9CLKs 7CLKs tRP 2CLKs 3CLKs 2CLKs tAC 5.4ns 6ns 6ns tO H 2.7ns 3ns 3ns H Y 5 7 V 6 4 1 6 2 0 H G (L)T-H C A S Latency 133MHz(7.5ns) 125MHz(8ns) 100MHz(10ns) 3CLKs 3CLKs 2CLKs tRCD 3CLKs 3CLKs 2CLKs tRAS 6CLKs 6CLKs 5CLKs tRC 9CLKs 9CLKs 7CLKs tRP 3CLKs 3CLKs 2CLKs tAC 5.4ns 6ns 6ns tO H 2.7ns 3ns 3ns Rev. 0.5/Jun.01 9 HY57V641620HG 4 Banks x 1M x 16Bit Synchronous DRAM H Y 5 7 V 6 4 1 6 2 0 H G (L)T-8 C A S Latency 125MHz(8ns) 100MHz(10ns) 83MHz(12ns) 3CLKs 2CLKs 3CLKs tRCD 3CLKs 2CLKs 3CLKs tRAS 7CLKs 5CLKs 6CLKs tRC 10CLKs 7CLKs 9CLKs tRP 3CLKs 3CLKs 2CLKs tAC 6ns 6ns 6ns tO H 3ns 3ns 3ns H Y 5 7 V 6 4 1 6 2 0 H G (L)T-P C A S Latency 100MHz(10ns) 83MHz(12ns) 66MHz(15ns) 2CLKs 2CLKs 2CLKs tRCD 2CLKs 2CLKs 2CLKs tRAS 5CLKs 5CLKs 4CLKs tRC 7CLKs 7CLKs 6CLKs tRP 2CLKs 2CLKs 2CLKs tAC 6ns 6ns 6ns tO H 3ns 3ns 3ns H Y 5 7 V 6 4 1 6 2 0 H G (L)T-S C A S Latency 100MHz(10ns) 83MHz(12ns) 66MHz(15ns) 3CLKs 2CLKs 2CLKs tRCD 2CLKs 2CLKs 2CLKs tRAS 5CLKs 5CLKs 4CLKs tRC 7CLKs 7CLKs 6CLKs tRP 2CLKs 2CLKs 2CLKs tAC 6ns 6ns 6ns tO H 3ns 3ns 3ns This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.5/Jun.01 HY57V641620HG COMMAND TRUTH TABLE A10/ AP OP code Command CKEn-1 CKEn CS RAS CAS WE DQM ADDR BA Note Mode Register Set H X L H L X H L L X H H L X X No Operation H X L H H X X Bank Active Read H X L X RA L V H Read with Autoprecharge Write H Write with Autoprecharge Precharge All Banks H Precharge selected Bank Burst Stop DQM Auto Refresh Entry Self Refresh1 Exit L H H H H X L H L H X CA H L V X L H L L X CA H H V X V X L L H L X X L X L H X H L X V X X X H L L L H L L X H X H X H X V X L L X H X H X H X V H H X X X X X H L H H X Entry Precharge power down Exit H L L H H X X X X L H H X X L V X X L H Clock Suspend Entry H L Exit L H N o te : 1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high 2 . X = D o n t c a r e , H = L o g i c H i g h , L = L o g i c L o w . B A = B a n k A d d r e s s , R A = R o w A d d r e s s , C A = C o l u m n A d d r e s s , Opcode = Operand Code, NOP = No Operation Rev. 0.5/Jun.01 11 HY57V641620HG P A C K A G E IN F O R M A T IO N 4 0 0 m i l 5 4 p i n T h i n S m all O u t l i n e P a c k a g e UNIT : mm(inch) 11.938(0.4700) 11.735(0.4620) 22.327(0.8790) 22.149(0.8720) 10.262(0.4040) 10.058(0.3960) 0.150(0.0059) 0.050(0.0020) 1.194(0.0470) 0.991(0.0390) 0.80(0.0315)BSC 0.400(0.016) 0.300(0.012) 5deg 0deg 0.597(0.0235) 0.406(0.0160) 0.210(0.0083) 0.120(0.0047) Rev. 0.5/Jun.01 12 |
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